Intel said that the second half will start producing “the most advanced in the industry” 10-nm solutions in the face of the Cannonlake processors. Company do not mind that TSMC, the manufacturer of processors for the iPhone, and Samsung has already begun mass production of 10-nm chips. According to the statement of Intel, none of the competitors are not able to produce such perfect 10-nm products, which are “a generation ahead” of competing solutions. In particular, we are talking about using the Hyper Scaling, which increases packing density and allows you to lay out twice as many transistors. To prove this, it honoured a senior researcher and Director of Intel process architecture mark Bohr talked about the methods of counting transistors on the chip.
Before the transition to each subsequent step led to doubling the density of the layout: on the same square crystal fit twice as many transistors. For example, it was during the transition from 90 nm to 64 nm and then to 45 nm and 32 nm. Recently, however, according to Bor, this is due to the growing complexity of further reducing the size — some companies have abandoned this rule, using all the lower numbers to denote the norms in minimal, if not absent increase the density of the layout. The result of the declared values do not show the real capabilities of the process and his position on the chart corresponding to Moore’s law.
Intel offers to determine the capabilities of process technology on a formula which includes the size of the model blocks is the simplest NAND cell and a more complex trigger — and the number of transistors in them. The relative prevalence of simple and more complex elements are reflected in the weights.
If every manufacturer will publish the value obtained by this formula for a particular process technology, will be able to compare different processes from one manufacturer and from different manufacturers. Companies involved in reverse engineering will be able to easily verify the declared value.
Intel claims that with the same dimensions as its chips are superior to competing solutions because accommodate twice as many transistors. This, in turn, leads to a decrease in chip area and “allows Intel to continue to follow Moore’s law”.
In the future, Intel plans to use an improved version of the 10-nm technology is shown at 10++, which will provide augmentation of productivity up to 15% and reducing energy consumption up to 30%.
“We always look at three generations from 7 to 9 years – said the Executive Vice President of Intel Stacy Smith. – As far as we can see, Moore’s law will live.”